Fixed
Created: Jul 8, 2016
Updated: Sep 8, 2018
Resolved Date: Jul 15, 2016
Found In Version: 7.0.0.15
Fix Version: 7.0.0.18
Severity: Standard
Applicable for: Wind River Linux 7
Component/s: Kernel
it seems that there is a conflict in bit position in WRL7 RCPL12:
see include/linux/spi/spi.h
#define SPI_MASTER_U_PAGE BIT(3) /* select upper flash */
#define SPI_MASTER_QUAD_MODE BIT(4) /* support quad mode */
#define SPI_MASTER_MUST_RX BIT(3) /* requires rx */
#define SPI_MASTER_MUST_TX BIT(4) /* requires tx */
SPI_MASTER_U_PAGE is in conflict with SPI_MASTER_MUST_RX : it shall be BIT(5).
SPI_MASTER_QUAD_MODE is in conflict with SPI_MASTER_MUST_TX : it shall be BIIT(6).
latest definitions from Xilinx github:
#define SPI_MASTER_HALF_DUPLEX BIT(0) /* can't do full duplex */
#define SPI_MASTER_NO_RX BIT(1) /* can't do buffer read */
#define SPI_MASTER_NO_TX BIT(2) /* can't do buffer write */
#define SPI_MASTER_MUST_RX BIT(3) /* requires rx */
#define SPI_MASTER_MUST_TX BIT(4) /* requires tx */
#define SPI_MASTER_U_PAGE BIT(5) /* select upper flash */
#define SPI_MASTER_QUAD_MODE BIT(6) /* support quad mode */
#define SPI_DATA_STRIPE BIT(7) /* support data stripe */
#define SPI_BOTH_FLASH BIT(8) /* enable both flashes */
/wrlinux-7/wrlinux/configure --enable-board=xilinx-zynq --enable-kernel=standard --enable-rootfs=glibc-std
check include/linux/spi/spi.h
