Wind River Support Network

Description

Problem Description
======================
Can't find /sys/devices/system/edac/mc/ in EDAC test.

Log location
======================
U-Boot 2011.12-00025-gc6d9d50 (Nov 19 2012 - 11:02:40)

CPU0:  P4080E, Version: 2.0, (0x82080020)
Core:  E500MC, Version: 2.0, (0x80230020)
Clock Configuration:
       CPU0:1499.985 MHz, CPU1:1499.985 MHz, CPU2:1499.985 MHz, CPU3:1499.985 MHz,
       CPU4:1499.985 MHz, CPU5:1499.985 MHz, CPU6:1499.985 MHz, CPU7:1499.985 MHz,
       CCB:799.992 MHz,
       DDR:649.994 MHz (1299.987 MT/s data rate) (Asynchronous), LBC:99.999 MHz
       FMAN1: 599.994 MHz
       FMAN2: 599.994 MHz
       PME:   599.994 MHz
L1:    D-cache 32 kB enabled
       I-cache 32 kB enabled
Board: P4080DS, Sys ID: 0x17, Sys Ver: 0x01, FPGA Ver: 0x0c, vBank: 0
36-bit Addressing
Reset Configuration Word (RCW):
       00000000: 105a0000 00000000 1e1e181e 0000cccc
       00000010: 40464000 3c3c2000 de800000 e1000000
       00000020: 00000000 00000000 00000000 008b6000
       00000030: 00000000 00000000 00000000 00000000
SERDES Reference Clocks: Bank1=100MHz Bank2=125MHz Bank3=125MHz
I2C:   ready
SPI:   ready
DRAM:  Initializing....using SPD
Detected UDIMM 9965525-008.A00LF
Detected UDIMM 9965525-008.A00LF
CS2 is disabled.
CS3 is disabled.
CS2 is disabled.
CS3 is disabled.
6 GiB left unmapped
8 GiB (DDR3, 64-bit, CL=9, ECC on)
       DDR Controller Interleaving Mode: cache line
       DDR Chip-Select Interleaving Mode: CS0+CS1
Testing 0x00000000 - 0x7fffffff
Testing 0x80000000 - 0xffffffff
Testing 0x100000000 - 0x17fffffff
Testing 0x180000000 - 0x1ffffffff
Remap DDR 6 GiB left unmapped

POST memory PASSED
Flash: 128 MiB
L2:    128 KB enabled
Corenet Platform Cache: 2048 KB enabled
SERDES: bank 2 disabled
SERDES: bank 3 disabled
SRIO1: disabled
SRIO2: disabled
MMC:  FSL_SDHC: 0
EEPROM: Invalid ID (ff ff ff ff)
PCIe1: Root Complex, no link, regs @ 0xfe200000
PCIe1: Bus 00 - 00
PCIe2: disabled
PCIe3: Root Complex, no link, regs @ 0xfe202000
PCIe3: Bus 01 - 01
In:    serial
Out:   serial
Err:   serial
Net:   Fman1: Uploading microcode version 101.8.0
Fman2: Uploading microcode version 101.8.0
PHY reset timed out
PHY reset timed out
PHY reset timed out
PHY reset timed out
FM1@DTSEC2, FM2@DTSEC1, FM2@DTSEC2, FM2@DTSEC3, FM2@DTSEC4

Environment size: 2903/8188 bytes
=> setenv hwconfig_bak 'serdes:fsl_srds_lpd_b2=0xf;fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1,ecc=on'
=> setenv hwconfig 'fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1,ecc=on;'
=> saveenv
Saving Environment to Flash...
Un-Protected 1 sectors
Erasing Flash...
. done
Erased 1 sectors
Writing to Flash... 9....8....7....6....5....4....3....2....1....9....8....7....6....5....4....3....2....1....done
Protected 1 sectors
=> printenv hwconfig
hwconfig=fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1,ecc=on;
=>


Wind River Linux 5.0.1.0 localhost console

localhost login: root
Password:
root@localhost:~# cd /sys/devices/system/edac/mc/
-sh: cd: /sys/devices/system/edac/mc/: No such file or directory
root@localhost:~# 

Steps to Reproduce

1.Configuration:
/lpg-build/cdc/fast_prod/wrlinux501/dvd_install/lx34_12sp/wrlinux-5/wrlinux/configure --enable-jobs=8 --enable-parallel-pkgbuilds=4 --enable-kernel=cgl --with-layer=/lpg-build/cdc/bsp/wrlinux-5.0.1/wr-testing/kts,/lpg-build/cdc/bsp/wrlinux-5.0.1/wr-testing/bts, --enable-test=yes --enable-rootfs=glibc-cgl --enable-board=fsl_e500mc --with-rcpl-version=0

2.BUild:
make fs

3.Set u-boot variable:
=> setenv hwconfig 'fsl_ddr:ctlr_intlv=cacheline,bank_intlv=cs0_cs1,ecc=on;'

4.Run case:
# cd /sys/devices/system/edac/mc/