Fixed
Created: Jan 11, 2019
Updated: Mar 27, 2019
Resolved Date: Jan 27, 2019
Found In Version: 10.17.41.13
Fix Version: 10.17.41.14
Severity: Standard
Applicable for: Wind River Linux LTS 17
Component/s: BSP
The following fix for pll clocks rate calculation is available upstream on altera-opensource and it is essential for Stratix 10 HPS to work correctly:
https://github.com/altera-opensource/linux-socfpga/commit/23d4f7b2c6000e095399a6266ef35c213f93649e
"The main PLL calculation has a mistake. We should be using the multiplying the VCO frequency, not the parent clock frequency."
We should add it into the product as well.
BSP: ./wrlinux-x/setup.sh --machines intel-socfpga-64b
To build the project:
./wrlinux-x/setup.sh --machines intel-socfpga-64b
set environment
copy attached local.conf in <prj-dir>/build/conf.local.conf
bitbake wrlinux-image-glibc-core
(for the image)
I have only checked that the source code has the vco_freq defined against parent_rate, not vco_freq
