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Fixed

LIN5-3774 : fsl_imx6: sabre lite(REV D) have not timer irq.

Created: May 20, 2013    Updated: Dec 19, 2017
Resolved Date: Jun 2, 2013
Found In Version: 5.0.1
Fix Version: 5.0.1.4
Severity: Standard
Applicable for: Wind River Linux 5
Component/s: BSP - Async

Description

## Booting kernel from Legacy Image at 10800000 
Image Name: Linux-3.4.34-WR5.0.1.0_standard
Image Type: ARM Linux Kernel Image (uncompressed)
Data Size: 4853024 Bytes = 4.6 MB
Load Address: 10008000
Entry Point: 10008000
Verifying Checksum  OK

Loading Kernel Image  OK
OK
Starting kernel 
Uncompressing Linux done, booting the kernel.
Booting Linux on physical CPU 0
Initializing cgroup subsys cpuset
Initializing cgroup subsys cpu
Linux version 3.4.34-WR5.0.1.0_standard (silee@silee) (gcc version
4.6.3 (Wind River Linux Sourcery CodeBench 4.6a-99) ) #1 SMP 
PREEMPT Thu Apr 4 00:02:58 KST 2013
CPU: ARMv7 Processor [412fc09a] revision 10 (ARMv7), cr=10c5387d
CPU: PIPT / VIPT nonaliasing data cache, VIPT aliasing instruction 
cache
Machine: Freescale i.MX 6Quad Sabre-Lite Board
Memory policy: ECC disabled, Data cache writealloc
PERCPU: Embedded 9 pages/cpu @8135f000 s14912 r8192 d13760 u36864
Built 1 zonelists in Zone order, mobility grouping on. Total pages: 227072
Kernel command line: console=ttymxc1,115200
PID hash table entries: 4096 (order: 2, 16384 bytes)
Dentry cache hash table entries: 131072 (order: 7, 524288 bytes)
Inode-cache hash table entries: 65536 (order: 6, 262144 bytes)
allocated 2097152 bytes of page_cgroup
please try cgroup_disable=memory option if you dont want memory cgroups
Memory: 640MB 256MB = 896MB total
Memory: 894684k/894684k available, 153892k reserved, 0K highmem
Virtual kernel memory layout:
vector : 0xffff0000  0xffff1000 ( 4 kB)
fixmap : 0xfff00000  0xfffe0000 ( 896 kB)
vmalloc : 0xc0800000  0xfb000000 ( 936 MB)
lowmem : 0x80000000  0xc0000000 (1024 MB)
modules : 0x7f000000  0x80000000 ( 16 MB)
.text : 0x80008000  0x808e6220 (9081 kB)
.init : 0x808e7000  0x80938a40 ( 327 kB)
.data : 0x8093a000  0x809a8ff0 ( 444 kB)
.bss : 0x809a9014  0x80a577e4 ( 698 kB)
SLUB: Genslabs=11, Hwalign=64, Order=0-3, MinObjects=0, CPUs=4,Nodes=1
Preemptible hierarchical RCU implementation.
NR_IRQS:436
sched_clock: 32 bits at 24MHz, resolution 41ns, wraps every 178956ms
MXC_Early serial console at MMIO 0x21e8000 (options 115200)
bootconsole [ttymxc1] enabled
Console: colour dummy device 80x30
Calibrating delay loop

Workaround

From b28f8c2f7ee0fe645339fc87b6adb3ccab176576 Mon Sep 17 00:00:00 2001
From: Zhong Hongbo <hongbo.zhong@windriver.com>
Date: Fri, 17 May 2013 18:30:07 +0800
Subject: [PATCH] imx6q: Add support to source GPT from 24MHz

On MX6Q TO1.1, MX6DL/S and MX6Solo, GPT can be sourced
from a constant source (better for frequency scaling).
Currently we set the GPT clock to 3MHz (24MHz div by 8).

Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
Signed-off-by: Zhong Hongbo <hongbo.zhong@windriver.com>
---
 arch/arm/plat-mxc/include/mach/mxc.h |    1 +
 arch/arm/plat-mxc/time.c             |   22 +++++++++++++++++++---
 2 files changed, 20 insertions(+), 3 deletions(-)

diff --git a/arch/arm/plat-mxc/include/mach/mxc.h b/arch/arm/plat-mxc/include/mach/mxc.h
index ab56a9a..7045245 100644
--- a/arch/arm/plat-mxc/include/mach/mxc.h
+++ b/arch/arm/plat-mxc/include/mach/mxc.h
@@ -217,6 +217,7 @@ int tzic_enable_wake(void);
 extern struct cpu_op *(*get_cpu_op)(int *op);
 #endif
 
+#define cpu_is_mx5()    (cpu_is_mx51() || cpu_is_mx53() || cpu_is_mx50())
 #define cpu_is_mx3()	(cpu_is_mx31() || cpu_is_mx35())
 #define cpu_is_mx2()	(cpu_is_mx21() || cpu_is_mx27())
 #define cpu_is_mx6()	(cpu_is_mx6q() || cpu_is_mx6dl())
diff --git a/arch/arm/plat-mxc/time.c b/arch/arm/plat-mxc/time.c
index f629c5d..1da30f0 100644
--- a/arch/arm/plat-mxc/time.c
+++ b/arch/arm/plat-mxc/time.c
@@ -317,6 +317,7 @@ static int __init mxc_clockevent_init(struct clk *timer_clk)
 void __init mxc_timer_init(struct clk *timer_clk, void __iomem *base, int irq)
 {
 	uint32_t tctl_val;
+	u32 reg;
 
 	clk_prepare_enable(timer_clk);
 
@@ -329,9 +330,24 @@ void __init mxc_timer_init(struct clk *timer_clk, void __iomem *base, int irq)
 	__raw_writel(0, timer_base + MXC_TCTL);
 	__raw_writel(0, timer_base + MXC_TPRER); /* see datasheet note */
 
-	if (timer_is_v2())
-		tctl_val = V2_TCTL_CLK_PER | V2_TCTL_FRR | V2_TCTL_WAITEN | MXC_TCTL_TEN;
-	else
+	if (timer_is_v2()) {
+		if (cpu_is_mx5() ||
+			mx6q_revision() == IMX_CHIP_REVISION_1_0)
+			tctl_val = V2_TCTL_CLK_PER | V2_TCTL_FRR |
+						V2_TCTL_WAITEN | MXC_TCTL_TEN;
+		else {
+			tctl_val = V2_TCTL_CLK_OSC_DIV8 | V2_TCTL_FRR |
+						V2_TCTL_WAITEN | MXC_TCTL_TEN;
+			if (!cpu_is_mx6q()) {
+				reg = __raw_readl(timer_base + MXC_TPRER);
+				reg |= (V2_TPRER_PRE24M_DIV8 <<
+							V2_TPRER_PRE24M_OFFSET);
+				__raw_writel(reg, timer_base + MXC_TPRER);
+				/* Enable the 24MHz input clock. */
+				tctl_val |= V2_TCTL_ENABLE24M;
+			}
+		}
+	} else
 		tctl_val = MX1_2_TCTL_FRR | MX1_2_TCTL_CLK_PCLK1 | MXC_TCTL_TEN;
 
 	__raw_writel(tctl_val, timer_base + MXC_TCTL);
-- 
1.7.9.5

Steps to Reproduce

run stand kernel on sabre lite board(REV D)

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